Adder/Multiplier Design and Metric Evaluation
نویسنده
چکیده
Many Arithmic Logic Unit (ALU) designs have been constructed and tested in order to optimized different functions in which the Computer Processing Unit (CPU) uses to carry out various operations. As is it used so often, it is important that the ALU function correctly, with high performance, and with low energy consumption. This paper reviews and analyses ten different ALU designs, focusing on metrics such as ALU performance, power dissipation, energy consumption, ITRS node technology and space complexity. One interesting ALU design that is mentioned is the 16-bit ALU that is designed to lower power dissipation and increase performance. Disabling the adder function while processing other functions was one feature that was enabled to achieve an energy consumption of 54mW [9]. This design also used pipelining to help decrease adder execution
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